A variety of timers exist for controlling the operating duty cycle of different types of load devices. One such representative type of load comprises the defrost mechanisms for various refrigeration circuits in which there are alternate "on" and "off" intervals of operation. Typically the control functions which may affect a defrosting operation in a refrigeration system include discontinuance of fan motor operation and/or reversal of the coolant flow valve and/or energization of a resistive heating element. In any event, the duty cycle is controlled by a duty cycle timer which, during the "off" interval, does not operatively energize the various defrost mechanisms and which, during the "on" interval does operate those defrost mechanisms. Various control philosophies dictate, to a certain extent, the type of defrost control timer or duty cycle timer which might be employed.
For instance, in some systems the load, such as a defrost mechanism, may not be energized unless and until some sort of sensing device determines its need. For instance, with a defrost mechanism the sensor may detect ice buildup. In some such instances, the defrost mechanism may be made operative only upon detection of the ice buildup and may then be maintained operative either for a predetermined interval or until a sensor determines that the triggering condition has abated. In other instances, which may not employ such a sensor, the defrost mechanisms may be maintained inoperative for a predetermined interval and then actuated to provide the defrost function for a second predetermined interval. It is to this latter type of load control philosophy that the present invention applies.
Specifically, the duty cycle timer is required to measure a predetermined "off", or inoperative, interval and to then effect turn-on of the load device and measure a second predetermined "on" interval following which the load is again turned off. In certain instances where the refrigeration condition which might lead to the defrost condition is itself satisfied, as by meeting the setting of a room temperature thermostat, some further provision may be made for halting or "holding" the count then registered by the timer during the particular "off" or "on" interval.
One form of timer often used in duty cycle timing is illustrated in U.S. Pat. No. 4,327,556. A timer motor driven by 60 Hz line voltage determines the duration of at least the "on" interval of the duty cycle and might also be used for determining the "off" interval. The cost of such timer motor may be significant in a control system of that sort.
With the advent of reliable, relatively low cost electronic devices, the utilization of electronic duty cycle timers has increased significantly. Typically, a single source of clock signals, for instance provided by an oscillator or 60 Hz line frequency, is utilized to drive one or more multistage electronic counters. In those instances in which only one of the two "off" and "on" intervals is to be timed, a single, multistage electronic binary counter is typically used. Where both the "off" interval and the "on" interval are to be timed, it is conventional for a single clock signal to drive either two separate "on" and "off" counters or a single multistage counter which determines both the "on" and the "off" intervals by signal outputs from a plurality of the stages of the multistage counter. In this latter instance, decoding logic may be utilized to decode the outputs of the counter stages. U.S. Pat. No. 3,890,798 discloses an electronic timer having first, second and third counters in which clock signals are applied to the input stage of the first counter and its outputs are utilized to drive the second and third counters.
A limitation with such systems is the dependence of both the "on" and the "off" intervals on a single clock source. Such dependence necessarily means that the "off" interval and the "on" interval are dependent upon one another as some binary function of the frequency of the clock source. Such interdependence may not be desirable, particularly where it necessitates extensive use of logic gating to decode various stages of a multistage counter to provide both the "on" and the "off" intervals. Disclosure of Invention
It is an object of the invention to provide an economical and relatively flexible duty cycle timer for controlling the duration of "off" and "on" intervals of a control signal. Included within this object is the provision of such an improved duty cycle timer suitable for use in controlling the defrost mechanism associated with a refrigeration circuit.
It is a further object of the present invention to provide an improved duty cycle timer which, when interrupted in its timing function, is capable of retaining the accumulated time-count and resuming the timing function therefrom.
In accordance with the present invention there is provided an improved duty cycle timer which provides a duty cycle control signal having alternate, complementary "on" and "off" intervals. The "on" and "off" intervals of the control signal are typically represented by different logic states. The timer utilizes integrated circuitry for providing first and second independent clock signals which respectively drive first and second electronic counters. One counter is used for determining the "off" interval and the other counter is used for determining the "on" interval. Completion of the count by each respective counter signifies completion of the respective duty cycle interval, and the respective outputs are cross-connected to the alternate counter to initiate the subsequent counting sequence by that alternate counter.
Although the "off" and the "on" intervals may be of equal duration, typically they are different. A singular duty cycle control signal having both "off" and "on" intervals is provided by output of a predetermined, i.e., final, stage of one of the counters. In an exemplary embodiment, the interval measured by the first electronic counter is longer than the interval measured by the second electronic counter, both counters have the same number of operative stages, the first clock is at a lower repetition rate than the second clock and the duty cycle control signal is provided by the final stage of the first counter.
In the illustrated embodiment, the first clock and first counter are incorporated in one integrated circuit chip and the second clock and second counter are incorporated in a second integrated circuit chip. Each of the counters may be reset by the output signal from the final stage of the opposite counter. The connection of selected values of resistance and capacitance to the respective integrated circuits determines the respective frequency of the respective clock.
The duty cycle control signal may be extended to the control electrode of an electronic switch for controlling the flow of electrical current to a load device, as for instance the defrosting mechanism associated with a refrigeration circuit. Further, operation of the first and second clock sources may be inhibited by an appropriate "hold" signal to interrupt the counting operation yet allow maintenance of the accumulated count in the respective counters. Circuitry is provided for converting the presence or absence of an AC signal, as from a thermostat, into a corresponding "enable or hold" logic level to respectively enable or inhibit operation of one or both of the clock sources.